The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 1995
Filed:
Nov. 23, 1993
Yukihiro Yoshida, Ikoma, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A multivalued adder for processing addition of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input circuit includes parallel inputs for binary logic and multivalued logic, and receives the first data. The first input circuit also outputs a first set of bit data representing the first data. Similarly, the second input circuit includes parallel inputs for binary logic and multivalued logic, and receives the second data. The second input circuit also outputs a second set of bit data representing the second data. An adding circuit, connected to the first and said second input circuits, adds the second set of bit data and the first set of bit data. An output circuit, connected to the adding circuit, converts the output of the adding circuit into data in binary logic and multivalued logic, in parallel, and outputs converted data in binary logic and multivalued logic, in parallel.