The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 1995
Filed:
Nov. 21, 1994
Applicant:
Inventors:
Manoj Kumar, Austin, TX (US);
George M Lattimore, Austin, TX (US);
Joseph M Poplawski, Jr, Austin, TX (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
327142 ; 327143 ; 327198 ; 326 94 ; 377 73 ; 377 78 ;
Abstract
A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.
Quick Actions:
Kumar, Manoj. (1995). Reset generation circuit to reset self resetting cmos circuits (U.S. Patent No. 5467037). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5467037
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile