Verifiable security circuitry for preventing unauthorized access to

Abstract

A security system is used for programmable read-only memory locations within a very large scale integrated (VLSI) circuit. In a first security bit memory location there is stored a first security data bit. The first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed. In a second security bit memory location there is stored a second security data bit. The second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed. A selection logic is electrically coupled to the first security bit memory location and the second security bit memory location. The selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal. An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal. The access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.