Phase-locked loop circuit with minimum output jitter and maximum

Abstract

A compact PLL circuit (100) and method of operation are provided which include a phase/frequency detector circuit (102), a control voltage generating circuit (110), and a VCO circuit (108) including at least one delay buffer circuit (118). A transmission gate (M3, M4) is arranged in series with each delay element (M5, M6) in the VCO circuit (108). A plurality of 'power down' transistors (M3, M8-M9, M13-M16) are arranged strategically in the control circuit (110), and a 'power down' transistor (M7) is arranged strategically in at least one delay buffer circuit (118). A filter arrangement (R1, R2, C) is included in the control circuit (110). Consequently, a relatively compact PLL circuit design is provided in which output jitter is minimized, the overall stability of the PLL is maximized, and only leakage current is drawn from the PLL circuit (100) during a 'power down' mode of operation.