The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 1995

Filed:

Apr. 30, 1993
Applicant:
Inventors:

Mitsuhiro Ishizuka, Tokyo, JP;

Hiroshi Saeki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J / ;
U.S. Cl.
CPC ...
313517 ; 313496 ;
Abstract

A chip-in-glass fluorescent indicator panel includes a glass substrate, a wiring layer, an insulating layer, a pattern-like graphite layer, a phosphor layer, a filament, a grid, an IC, an IC shield, a filament fixing portion, and an anchor. The wiring layer is formed on the glass substrate. The insulating layer covers the wiring layer. The pattern-like graphite layer is formed on the insulating layer to be electrically connected to the wiring layer. The phosphor layer is formed on the pattern-like graphite layer. The filament is suspended above phosphor layer with an interval. The grid is arranged between the filament and the phosphor layer. The IC is fixed on the insulating layer on one end side of the glass substrate to be connected to the pattern-like graphite layer through the wiring layer. The IC shield is arranged between the IC and the filament. The filament fixing portion is formed on the IC shield. The anchor is arranged on the insulating layer on the other end side of the glass substrate to suspend the filament between the anchor and the filament fixing portion.


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