The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 1995
Filed:
Jan. 13, 1993
Gideon Wertheizer, Petach-Tikva, IL;
Yair Be'ery, Petach-Tikva, IL;
Bat-Sheva Ovadia, Herzeliya, IL;
Yael Gross, Tel-Aviv, IL;
Ronen Perets, Ramat-Gan, IL;
Yakov Milstein, Natanya, IL;
DSP Semiconductors Ltd, San Jose, IL;
DSP Semiconductors USA, Inc., San Jose, CA (US);
Abstract
An improved cyclical buffer having an integer M number of memory locations in respect of which a number STEP of consecutive memory locations are required to be accessed in a single operation and having a predetermined START location defining an initial memory location to be accessed. M is constrained to be an integer multiple of STEP and the k least significant bits of START are zero where k is the minimal integer satisfying the relation 2.sup.k >M-.vertline.STEP.vertline.. The result is the same as the general MODULO algorithm employed in conventional cyclical buffers but without the cost of implementing the complete MODULO function. An apparatus for generating successive addresses involves an ADDER and a k-bit COMPARATOR coupled via a MULTIPLEXER to an address register such that the k-least significant bits of the ADDER or M-.vertline.STEP.vertline. or 0 is fed to the k-least significant bits of the address register depending on the output of the k-bit COMPARATOR.