The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 1995

Filed:

Jul. 11, 1994
Applicant:
Inventor:

Shuji Yamamoto, Osaka, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371-51 ; 371-53 ;
Abstract

A circuit structure for expanding the width of a plurality of error pulses detected in the data of one frame during digital transmission is described. A plurality of error pulses are counted by a counting circuit and the counted value is inputted to a pulse generating circuit. The pulse generating circuit outputs the frequency-divided clock pulses outputted from the frequency dividing circuit as many as the counted value. The frequency-divided clock pulse is obtained by dividing the frequency of the reference clock pulse of data with a predetermined rate and this frequency-divided clock pulse is outputted from the pulse generating circuit as the error pulse. The error pulse expanded in time only during such a frequency dividing period is very useful for improving the reliability of error rate detection.


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