Apparatus for argument reduction in exponential computations of ieee

Abstract

An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.<1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to 'zero' and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS). Also incorporated is a leading zero detector/encoder circuit and a second circuit arrangement operative to perform pipeline operations on exponents connected to an encoder circuit whose output controls the aligner circuit and a selector circuit driven by the outputs of the detector/encoder circuit and encoder circuit whose output controls the normalizer circuit; a xi determining circuit that generates the xi mantissa on a xi-BUS connected to the first circuit arrangement such that: mantissa xi=0=K(1) K(2) 1 0 . . . , 0, and a read-only memory to store the F(xi) values whose output is connected to inputs of the first and second circuits for the respective mantissa and exponent parts of F(xi).