The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 1995

Filed:

Dec. 12, 1994
Applicant:
Inventors:

Steven C Jones, Garland, TX (US);

Subhashish Mukherjee, Bangalore, IN;

Stephen C Kwan, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ; H03F / ;
U.S. Cl.
CPC ...
330253 ; 330307 ;
Abstract

An amplifier, preferably an integrated circuit, capable of accepting input common mode voltages below the circuit reference voltage or substrate voltage in the case of an integrated circuit. The amplifier comprises a differential voltage input having higher and lower voltage terminals, a first NMOS transistor coupled between a voltage supply and the higher voltage terminal and a second NMOS transistor coupled between the voltage supply and the lower voltage terminal. A third NMOS transistor is coupled between the voltage supply and the first transistor gate, a fourth NMOS transistor is coupled between the voltage supply and the second transistor gate and a sink resistor is coupled between the gate of the second transistor and the lower voltage terminal. A differential resistor is coupled between the gates of the first and second transistors. The first and second transistors include a source and a backgate coupled to each other and electrically isolated from the substrate with the source of each of the first and second transistors being coupled to a different one of the input terminals. The third and fourth transistors include a source and a backgate coupled to each other and electrically isolated from the substrate with the source of each of the third and fourth transistors coupled to opposite ends of the differential resistor. The circuit further includes a PMOS mirror circuit for providing an output.


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