High-speed semiconductor gain memory cell with minimal area occupancy

Abstract

A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor. Alternatively, the present invention can be realized with three transistors where the memory cell includes: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.