The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1995
Filed:
Aug. 11, 1994
Chong M Lin, Sunnyvale, CA (US);
Tatao Chuang, San Jose, CA (US);
Tran Long, San Jose, CA (US);
Hy Hoang, San Jose, CA (US);
Seiko Epson Corporation, Suwa, JP;
Abstract
A power bus having power slits embodied therein. The present invention includes three embodiments. The first embodiment is directed to generic power buses. Each power bus has a first axis, along which power flows, and a second axis. Each of the power slits have an identical maximum width and minimum length. Power slits located along the first axis are separated from one another by a first minimum value, and power slits located along the second axis are separated from one another by a second minimum value. The first and second minimum values are selected as a function of electron flow and photolithography. The second embodiment is a continuation of the first embodiment and is directed to an apparatus with a plurality of power buses in which two buses overlap at 90.degree. angles. The overlap area of the apparatus is void of power slits, but has holes at intersection points of a set of pointer lines. The pointer lines are imaginary lines eminating from the power slits. The third embodiment is directed to an apparatus with a plurality of power buses in which two power buses overlap at a non-orthogonal angle. The overlap area in this third embodiment is generally identical to that of the second embodiment.