The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1995
Filed:
Jan. 27, 1994
Yoshitaka Taki, Kawasaki, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal from the storage/average unit with an output signal from the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit. Therefore, a transition period determined from a power ON state to a stable state can be reduced, and further, an original clock signal can be obtained and output by removing any noise components from a clock signal.