Semiconductor device interconnect layout structure for reducing

Abstract

In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow. In a second approach, an interconnect level (50) is formed of a polycrystalline material and connects two points in the semiconductor device using essentially only a plurality of branches (52) each having a linewidth (W) less than the median grain size of the polycrystalline material. In a third approach, an interconnect run (60) consists essentially of a plurality of upper and lower straps (62,64) connected by a plurality of interlevel connectors (66) so that a chain is provided which connects substantially the full length between two points in the semiconductor device.