Dual-port memory with selective read data output prohibition

Abstract

A dual-port memory is interposed between a host system and a slave system in a multiprocessor system, and data transmission between the host system and the slave system is performed through the dual-port memory using first and second input/output ports, the dual-port memory being accessible from the host system and the slave system simultaneously. An address region of the dual-port memory is placed overlapping the address space of an internal memory of the host system, so that no change is needed in programming in the host system, however, data collision may be generated in a region in the address space shared by the internal memory and the dual-port memory. In order to prevent data collision, the dual-port memory includes a memory cell array having a plurality of memory cells, first cell selection circuitry and second cell selection circuitry, and read data output prohibiting circuitry which prohibits data read out from a selected memory cell from being output to the host system. The output of data read out from a portion of the memory cells in the memory array may be prohibited instead.