Timing and gain control circuit for a prml read channel

Abstract

Method and apparatus for controlling the timing of the sampling of signals and signal amplitude in a PRML read channel. A VCO generates a read clock and a clock generator connected to the VCO generates even and odd clock signals corresponding to even and odd cycles of operation of the VCO. Serially connected even sample and hold circuits respond to clock signals to store samples of the read channel signal taken during successive odd cycles and serially connected odd sample and hold circuits store samples taken during successive even cycles. Comparator circuits compare the samples taken in each cycle to reference signals and the comparisons are clocked through two stage, even and odd shift registers to provide estimates of the presence or absence of nonzero samples for each even and odd cycle. Even and odd time error generators connected to the sample and hold circuits and, via AND gates enabled during even and odd cycles respectively, to the shift registers, generate even and odd time error signals from the samples and estimates during even and odd cycles respectively. An adder transmits the even and odd time error signals to the VCO input. Even and odd gain error generators connected to the sample and hold circuits and the AND gates generate even and odd gain error signals transmitted to a variable gain amplifier in the read channel.