Simple digital method for controlling digital signals to achieve

Abstract

A simple digital method is disclosed for controlling the digital signals sent out from a pluralities of identical signal processors (i.e, signal generators) so as to achieve synchronization. The method comprises the steps of: (a) obtaining a gate array logic circuit containing a plurality of pairs of comparison terminals and reference terminals, each of the comparison terminals is connected to a respective signal processor and the reference terminals are respectively connected to at least two different signal processors; (b) performing a gate array logic circuit operation, which comprises the following sub-steps: (i) performing a waiting procedure for each pair of comparison terminal and reference terminal until it is received that the comparison terminal is '1' and the reference terminal is '0', then moving to a gate procedure; otherwise, continuing the waiting procedure (i.e., no disable signal is sent out); (ii) performing a gate procedure by continuously sending out a '1' gate signal, i.e., the gate being set at '1' state (i.e., disable signal), until a '1' signal is received at the reference terminal is '1', then moving to a reset procedure; (c) performing a reset procedure by sending out a '0' gate output, i.e., the output gate being set at '0' state, the reset procedures continues until the reference terminal is '0', then going back to said waiting procedure; wherein a '0' gate signal indicating that system synchronization is normal, thus no disable action is taken, and a '1' gate signal indicating that one of the signal generators connected to a specific comparison reference is too fast and a disable action is taken. No disable action is taken during either the 'waiting' or the 'resetting' procedure; however, only the waiting procedure can be switched to the gate procedure (i.e., a disable action being taken).