The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 1995
Filed:
May. 23, 1994
Varkey P Alapat, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A memory array such as an EPROM device includes circuitry that permits testing of a I/O portion of the device without writing data to the EPROM. A data program block that applies a data dependent high voltage pulse to a selected column line for programming can be set to programming or test mode. In the normal, or programming mode, the data input to the data program block is output to the EPROM memory array as is normally required to write to the device. In the test mode, the data output from the data program block controllably connects or decouples the array input line to ground depending upon a binary state of the the input signal. A test output is evaluated using the same sense amp used to evaluate data read from a memory cells of the EPROM array during normal read operations. To prevent writing to the memory cells of the memory array during test, the programming voltage supply is prevented from being applied to a selected column line and all rows in the memory array are deselected simultaneously.