The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 1995
Filed:
Jul. 21, 1993
Applicant:
Inventor:
Shinji Hattori, Higashi-Osaka, JP;
Assignee:
Sharp Kabushiki Kaisha, Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327278 ; 327288 ;
Abstract
A CMOS pulse delay circuit is arranged to accurately delay an input pulse signal by a predetermined period. The CMOS pulse delay circuit provides two inverters for causing delays. The inverters each have switching transistors. The switching transistors of the first inverter are associated with voltage-controllable variable resistance elements located in series to each other for varying the on-resistance of the transistors. The varying of the on-resistance results in keeping the output delay phases accurate.