Compact phase recovery scheme using digital circuits

Abstract

The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag. The output of the six bit counter is the input to a four bit counter which provides a digital signal that controls the relative phase difference between the clock signal and the data signal. In a first implementation, the digital filter provides a data retiming function by sending the output of the four bit counter to a digital delay element interposed between the data signal input and the input to the phase comparator. When the data is out of phase with respect to a local clock, the digital filter determines from a multitude of binary phase decisions the polarity of phase correction required, and feeds this back to the delay element. The delay element then adjusts the phase of the incoming data with respect to the phase of the local clock. In a second implementation of the present invention, the digital filter provides a phase lock loop function by sending the output of the four bit counter to a digital to analog converter (DAC). The DAC adjusts the output frequency of a voltage controlled oscillator (VCO). The output of the VCO is the data input to the phase comparator and the data signal is the clock input to the phase comparator. The VCO output is compared to the data signal in order to adjust the frequency and phase of the VCO and generate the proper clock signal from the incoming data.