The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 1995
Filed:
Nov. 29, 1993
John C Bellamy, Coppell, TX (US);
DSC Communications Corporation, Plano, TX (US);
Abstract
A desynchronizer (10) for eliminating output mapping jitter includes a demapper circuit (12) for reading asynchronous data and a clock rate of an embedded signal within a synchronous channel (14). Payload data from the embedded signal is buffered within an elastic store circuit (17). The demapper circuit (12) outputs bit stuff and pointer justification timing adjustments to an overhead gapfill circuit (19) and a pointer justification leaky accumulator circuit (20). The overhead gapfill circuit (19) calculates overhead gaps within the payload data in order to generate a gapfill value (34). The pointer justification leaky accumulator circuit (20) determines the bit stuffs and pointer justifications occurring in the payload data in order to produce an accumulated value (36). The gapfill value (34) and accumulated value (36) are combined with an elastic fill value (18) from the elastic store circuit (17) in order to eliminate instantaneous variations within the elastic fill value (18) due to overhead gaps within the payload data and reduce the effect of bit stuff and pointer justification timing adjustments within the elastic fill value (18). An adjusted fill value is fed to a low pass filter (30) and a voltage controlled oscillator (32) of a clock recovery phase lock loop circuit (29). The clock recovery phase lock loop circuit (29) generates an output clock signal for transmitting the payload data from the elastic store circuit (17) without any mapping jitter due to overhead gaps and a reduction in jitter caused by timing adjustments.