Charge metering sampling circuit and use thereof in tft/lcd

Abstract

A circuit for sampling monotonic input voltage changes and holding an output precisely derived from the sampled input change. The output change may be of the same polarity as the input, or inverted, and in the inverting mode of operation may exhibit highly accurate gain or attenuation. A single complementary metal-oxide-semiconductor (CMOS) embodiment may be configured to operate with positive or negative input changes and to present normal or inverted outputs, according to the application of various clock or control signals. Alternatively, subsets of that circuit provide subsets of the operating modes. The circuit operates by adding measured amounts of charge to, or removing it from a capacitor under the control of the input signal. Additional functional capabilities are capture and hold of input maximum or minimum, and accurate setting or restoration of the dc level of the output. Multiple stages may be cascaded, and the circuit may be designed for large bandwidth without introducing pedestal errors due to channel charge.