The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 1995
Filed:
Nov. 10, 1993
Nobuo Tamba, Ohme, JP;
Masanori Odaka, Kodaira, JP;
Toshiro Hiramoto, Menlo Park, CA (US);
Masayuki Ohayashi, Hamura, JP;
Kayoko Saito, Hamura, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced. Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion. Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.