The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 1995

Filed:

Feb. 15, 1994
Applicant:
Inventors:

Masahiro Tamaki, Itami, JP;

Kouji Aono, Itami, JP;

Sinichi Sakamoto, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437226 ; 437902 ; 437947 ;
Abstract

A method for producing semiconductor chips includes preparing a semiconductor wafer having opposite front and rear surfaces and active semiconductor devices disposed in the semiconductor wafer at a part of the front surface, attaching a glass plate to the front surface of the semiconductor wafer, thinning the semiconductor wafer to a desired thickness from the rear surface, forming a first radiating layer over the rear surface of the semiconductor wafer, selectively forming a second radiating layer on the first radiating layer using, as a mask, a photoresist pattern covering portions of the first radiating layer opposite dicing regions, removing the semiconductor wafer from the glass plate, and cutting through the wafer and the first radiating layer with a dicing blade to produce a plurality of semiconductor chips. In this method, since the first radiating layer supports the thin wafer, the glass plate can be removed before the dicing process. Therefore, electrical testing of the semiconductor devices included in the wafer can be carried out before the wafer is divided into chips.


Find Patent Forward Citations

Tamaki, Masahiro. (1995). Process for dicing a semiconductor wafer having a plated heat sink using (U.S. Patent No. 5457072). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5457072

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