The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 1995
Filed:
Sep. 17, 1993
Brian Murphy, Brombach, DE;
Martin Zibert, Heufeld, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source. The MOS-transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS-transistor is conducting.