The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 1995
Filed:
Dec. 06, 1993
Walford W Ho, Saratoga, CA (US);
Chao-Chiang Chen, Cupertino, CA (US);
Yuk Y Yang, Foster City, CA (US);
Intelligent Logic Systems, Inc., Saratoga, CA (US);
Abstract
A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.