Semiconductor integrated circuit with external clock signal and reduced

Abstract

A semiconductor integrated circuit has a clock input buffer, a set of clock drivers, an input buffer, an input latch, an output latch, and a three-state buffer. The clock input buffer produces a first intermediate clock signal in phase with an external clock signal and a second intermediate clock signal out of phase with the external clock signal. With the first intermediate clock signal applied, the set of clock drivers produce non-overlapping two internal clock signals, namely, a first internal clock signal in phase with the external clock signal and a second internal clock signal out of phase with the external clock signal. The input latch is controlled by either the first internal clock signal or the second internal clock signal and latches an output of the input buffer connected to an input/output terminal. The output latch is controlled by the second intermediate clock signal and the latch control signal and latches a signal to be outputted. The three-state buffer outputs an output of the output latch to the input/output terminal. It is possible to reduce, with respect to the external clock signal, the delay time of the data output from the data input/output terminal and also to reduce, for the multi-bit data input/output terminals which operate simultaneously, the output delay time and its variations.