High density data compression encode/decode circuit apparatus and method

Abstract

Data compression encoding and decoding circuitry which eliminates the need for decode circuitry that looks for the flux reversal points, or peaks, namely the peak detector and the phase-lock-loop circuitry combination. The encoding circuitry manipulates data by encoding data in a pulse position modulation (PPM) format such that ONE's (1's) in a data stream are delayed a first predetermined time period from the prior flux reversal (transition), and the ZERO's (0's) in the data stream are delayed a predetermined second time period from the previous transition. The encoder includes timing delay calibration circuitry that controls the time difference between transitions representing ONE's and ZERO's. The timing difference being controlled by a phase-lock loop (PLL)/precision crystal oscillator circuit combination that provides a reference delay for use by ASIC delay elements. The reference delay essentially calibrates a plurality of ASIC delay elements for encoding and facilitate subsequent decoding of corresponding calibrated delay measurement of the data bits in the decoder. The decoder member includes a plurality of delay elements that are controlled by a similar PLL delay control circuit combination that facilitates placing a data bit into its proper decode value. The encoding and decoding circuitry facilitates a 200 MBPS data rate system which is usable in local area network (LAN) systems and further facilitates data throughput as high as 98%.