Constant cmos delay circuit

Abstract

A delay circuit comprises first modified inverter circuits, a first compensating circuit, second modified inverter circuits and second compensating circuit. Each first modified inverter circuit is composed of a CMOS inverter and an additional NMOS transistor. The CMOS inverter has an NMOS and a PMOS transistor connected in complementary connection between a positive power supply and ground. The additional NMOS transistor controls the current from the first modified inverter circuit to the ground. The first compensating circuit is connected to the gate of each additional NMOS transistor to supply an output signal for compensating a change in characteristic of the additional NMOS transistors. Each second modified inverter circuit is composed of a CMOS inverter and an additional PMOS transistor. The additional PMOS transistor controls a current from the second modified inverter circuit to the positive power supply. The second compensating circuit is connected to the gate of each additional PMOS transistor to supply an output signal for compensating a change in characteristic of the additional PMOS transistors. The first modified inverter circuits and the second inverter circuits are connected to each other to provide an output signal from the delay circuit which is delayed relative to an input signal into the delay circuit. The delay circuit may have a constant delay time event with variations in MOS transistor characteristic (Vth) and in ambient temperature.