The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 1995

Filed:

Sep. 10, 1993
Applicant:
Inventors:

Terry J Parks, Round Rock, TX (US);

Thomas H Holman, Jr, Austin, TX (US);

Assignee:

Dell USA, L.P., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395726 ; 3642281 ; 3642384 ; 364240 ; 364243 ; 3642434 ; 36424341 ; 3642468 ; 364D / ; 395427 ;
Abstract

A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.


Find Patent Forward Citations

Parks, Terry. (1995). Processor and cache controller interface lock jumper (U.S. Patent No. 5452463). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5452463

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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