Multi-processor system with fault detection

Abstract

A bus coupling type multi-processor system is disclosed having multiple processor modules and a fault detection system. A processor module includes a first processor, a second processor, and a monitor including a timer for measuring elapsed time, a register for storing a flag indicating the operation of its own processor, and a detector for detecting a fault either in its own processor or in another processor module. A starting circuit starts the second processor one clock period later than the first processor. A comparator compares the output from the first processor with the output of the second processor to detect a fault. A flag is set by its own processor module and is reset by a signal from another processor module. When a flag set by a first processor module is not reset by a second processor module, the monitor circuit in the first processor module detects this and judges that a fault has occurred in the second processor module. When a flag in a first processor module is not set within a predetermined time, the monitor circuit in a second processor module detects this and judges that a fault has occurred in the first processor module.