Packet data recovery system

Abstract

An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control circuit, a sample selector, and a sample circuit. The devices may be constructed on a single semiconductor substrate and may be connected to a bus structure having a microcomputer and a plurality of boards coupled to it. The delay locked loop circuit generates accurate delayed clock signals based on the reference clock. A positive edge synchronizer circuit, within the delay locked loop, serves as a programmable phase adjust for the sampling system. The positive edge synchronizer ensures proper phase relationship between the chosen delayed clock signal and the incoming data across semiconductor process variations. Packet enable circuit informs the delayed control circuit and the sample circuit when a start bit or stop bit is initiated in a data packet and enables those circuit blocks accordingly. The delayed selector control circuit uses the delayed clock signals to detect a start bit on a data signal. The delayed selector control circuit employs the data signal, delayed appropriately, as a metastability hardener to eliminate potential metastability problems associated with coincident data and delay locked loop signal waveforms. The sample selector, in response to detection of the start bit by the delayed selector control circuit, selects two sampling signals from the delay locked loop circuit for even bit and odd bit sampling in the sample circuit.