Method for monitoring symmetrical two-wire bus lines and two-wire bus

Abstract

A method for monitoring symmetrical two-wire bus lines and two-wire bus interfaces and a device for carrying out the method provides pulse weighting of low to high transitions or high to low transitions of the two wires operated in phase opposition of a two-wire bus line. The pulse chains thus obtained are used for step sequencing. In each case, one multistep shift function which is assigned to the first bus wire, is supplied with a first, constant logic read in state and can be reset to a second logic state in all-step fashion and, for all-step resetting of a similar second multistep shift function assigned to the second bus while, and vice versa, the step last achieved for each multistep shift function characterizing the respective fault state of the other bus wire. The pulse weighting is achieved by differentiation or high-pass filtering or by pulse generation controlled by state transition. For the pulse weighting, the device uses simple RC elements or edge-controlled monostable times, and for the multistep shift functions, two similar shift registers are used which can be loaded serially and clocked and reset in parallel and which can also be realized in one piece as a component of a monolithic semiconductor circuit by the previously mentioned elements. The device has a fault tolerance which can be programmed with respect to the bit width, and in conjunction with a likewise settable input cutoff frequency permits the decentralized local testing of two wire bus-type networks. The device can be made using CMOS technology, in conjunction with a very low space requirement.