Dual mode on-chip high frequency output structure with pixel video

Abstract

A dual mode high frequency output structure for a CCD image sensor has a differencing mode for determining a difference between a charge of successive charge packets of a first pulse train outputted from a shift register of the CCD image sensor and a non-differencing mode for outputting a video signal from the shift register of the CCD image sensor. The structure comprises a first series of CCD gates, a second series of CCD gates, an output well potential, a first clock for creating and shifting a first barrier and gradient in the first series of CCD gates for transferring a charge packet from the shift register to the output well, a second clock for creating and shifting a second barrier and gradient in the second series of CCD gates for transferring the charge packet from the output well potential to an output drain, an amplifier for amplifying an output voltage from the output well potential, a pre-set clock for pre-setting the amplifier to a pre-set voltage while the charge packet is in the output well potential until the charge packet is transferred therefrom. An asynchronous pass of successive charge packets through the output well produces the output voltage at the output well which is proportional to the difference between charges of the successive charge packets. A synchronous pass of the charge packets produces the output voltage for the video signal.