The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 1995

Filed:

Apr. 19, 1994
Applicant:
Inventor:

Kenneth Kosai, Goleta, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01J / ;
U.S. Cl.
CPC ...
2503384 ; 250332 ; 25037008 ; 374178 ; 374184 ; 257290 ;
Abstract

An uncooled thermal detector (10) includes a MIS capacitor (12) that is suspended from a material (26, 26a) having a low thermal conductivity. The MIS capacitor includes a doped semiconductor body portion (14) having a gate dielectric (20), a gate electrode (22), and a second electrode (24) disposed over a surface thereof. In operation, the capacitance of the MIS capacitor at a frequency near a high-frequency/low-frequency transition is measured or sensed. As the temperature of the MIS capacitor increases, the sensed capacitance increases because minority carriers are able to respond faster to a modulating gate voltage. Similarly, if the temperature decreases, the sensed capacitance decreases, because the minority carriers respond more slowly. A high thermal coefficient of capacitance (> 20%/K) is achieved at all gate bias values for which the MIS capacitor is in inversion. By a suitable choice of doping level and the introduction of a deep level (24) to control the minority-carrier lifetime, the transition frequency may be tailored to a desired operating frequency at a given temperature. A method for fabricating the uncooled detector, and an array of same, within a Si film (2) of an SOI wafer (1) is also disclosed.


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