The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1995

Filed:

Dec. 07, 1992
Applicant:
Inventors:

Luis J Garces, Raleigh, NC (US);

James W Sember, Zebulon, NC (US);

Assignee:

Square D Company, Palatine, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M / ;
U.S. Cl.
CPC ...
363 41 ; 363 58 ; 363 98 ; 363132 ;
Abstract

A closed loop pulse width modulator (PWM) inverter corrects for variations and distortion in the output AC voltage waveform caused by non-linearities of the switching devices or changes in the DC link voltage. A signal is generated that is a volt-seconds representation of the voltage error between a voltage command and the actual AC output voltage of the PWM inverter. The volt-seconds error signal becomes a controlling means in the closed loop of the PWM inverter to regulate the output AC voltage of the PWM inverter. Another signal that represents changes in the DC link voltage also modifies the voltage command signal. The system will compensate for the non-linear behavior of the PWM inverter due to deadtime, minimum on-times and off-times, and DC link voltage variations and voltage drops across the switching devices, and will also allow the operation of the inverter in a linear fashion for the region of operation when one or more of its phases are saturated, i.e., either full on or full off.


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