The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1995

Filed:

Feb. 14, 1994
Applicant:
Inventors:

Christina M Boyko, Conklin, NY (US);

Francis J Bucek, Binghamton, NY (US);

Richard W Carpenter, Johnson City, NY (US);

Voya R Markovich, Endwell, NY (US);

Darleen Mayo, Knightdale, NC (US);

Cindy M Reidsema, Austin, TX (US);

Joseph G Sabia, Norwich, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ; H05K / ; B05D / ;
U.S. Cl.
CPC ...
361792 ; 361743 ; 361795 ; 361778 ; 174260 ; 174261 ; 174262 ; 174263 ; 29830 ; 427 96 ; 427 97 ; 257698 ; 257700 ;
Abstract

The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.


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