The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 1995
Filed:
Sep. 22, 1993
Atsushi Ueoka, Moriguchi, JP;
Akinori Hiramatsu, Ikoma, JP;
Hiroyuki Sako, Hirakata, JP;
Kazuhiro Gotoh, Hirakata, JP;
Matsushita Electric Works, Ltd., Osaka, JP;
Abstract
A power supply with an inverter capable of avoiding the inverter from producing excessive high voltage when a load is detached or the load impedance is greatly increased. The inverter is energized by a fixed DC voltage source and includes at least one switching element and an L-C resonant circuit. The switching element is driven to turn on and off and cooperative with the L-C resonant circuit to produce a high frequency AC voltage at an inverter output for driving a load. The inverter includes first and second clamping diodes connected in series across the DC voltage source in anti-parallel relation thereto with the first and second diodes defining therebetween a first connection point. Also included in the inverter is a pair of first and second impedance elements which are connected in series across the inverter output to provide a divided voltage indicative of an output voltage of the inverter with the first and second impedance elements defining therebetween a second connection point. The first and second connection points are connected to each other so as to keep the points at a voltage level nearly equal to a fixed voltage of the DC voltage source, in such a manner as to limit the output voltage of the inverter below a predetermined level by allowing a clamping current to flow through the first and second diodes and impedance elements and through the DC voltage source to escape the excessive voltage developed in response to the increase in the impedance of the load.