Integrated circuit microprocessor with programmable chip select logic

Abstract

An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.