The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 1995
Filed:
Aug. 22, 1994
Charles M White, Noblesville, IN (US);
William A Lagoni, Indianapolis, IN (US);
Thomson Consumer Electronics, Inc., Indianapolis, IN (US);
Abstract
A differential current source (50) provides first and second complementary output currents (I1, I2) responsive to a video input signal (S1) which are coupled via respective load networks (52,54) to a common supply terminal (22) and develop first and second complementary video output signals (V1,V2). A first output circuit (56) applies the first output signal to a first output terminal (16) via a voltage follower transistor (Q6) and applies the second output signal to the first output terminal via a current source transistor (Q8). A second output terminal (18) is similarly driven by a second voltage follower transistor (Q5) and a second current source transistor (Q7), all transistors being of the same conductivity type. A tri-state control circuit (Q1,Q2) coupled to the differential current source enables the differential current source in a first operating mode to produce the first and second complementary currents whereby push pull output signals are produced at the output terminals. In a second operating mode, the tri-state control circuit forces the complementary currents to zero whereby the common supply terminal (22) applies turn-off bias via the two load networks to the control electrodes of all of the output transistors thereby 'tri-stating' (isolating) the output terminals. Advantageously, in the tri-state mode, there is zero quiescent power dissipation in the output circuits, the load networks, the differential current source and the tri-state control circuit.