The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 1995
Filed:
Aug. 17, 1994
Geary L Leger, Fremont, CA (US);
Cirrus Logic, Inc., Fremont, CA (US);
Abstract
The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform. DC offset compensation of the encoded waveform is either removed prior to data decoding or after a data pre-decoding step; in either case the apparatus searches and detects predetermined substituted patterns in order to correct for the inversion or substitution. Further, a clock state generator is disclosed that uses precision silicon delays in order to generate clock states and quickly synchronize the states to the received encoded waveform. The clock states generate the recovered clocks required to decode data from the encoded waveform.