Frame rate conversion with asynchronous pixel clocks

Abstract

A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.