The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 1995
Filed:
Nov. 13, 1991
Jerry R Van Aken, Sugar Land, TX (US);
Chenwei J Yin, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the n.sup.th first AND gate 126 coupled to the n.sup.th one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an n.sup.th one of the second AND gates 128 coupled to a (j-n+1).sup.th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an m.sup.th one of the OR gates 130 being coupled to the output of an m.sup.th one of the first AND gate 126, the second input port of an n.sup.th one of the OR gates 130 coupled to the output of the n.sup.th one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j.