Digital motor communication circuit and method

Abstract

A method and circuit for generating a commutate signal required to control the spindle motor. The spindle motor generates a BEMF signal which transitions periodically between states. This signal is used to generate a synchronizing pulse at the transitions of the BEMF signal. The synchronizing pulse resets a counter which incrementally counts a value at each clock pulse of the circuit. When a BEMF transition is received, a maximum count value for the BEMF period is determined and the counter is reset to zero. The maximum count value is then divided in half, preferably by a right shifting binary representation of the maximum count value by one bit, thereby dividing the value by one-half, and is input to a register. The value equal to one-half of the maximum count value is then outputted from the register at each subsequent clock pulse to a comparator. Also output is the current count generated by the counter. Thus when the curent counter value equals the value stored in the register, a pulse is generated. This pulse, referred to as the A.dbd.B pulse, is then used to generate the commutate signal. The present invention therefore ensures that the commutate signal is always generated halfway between transitions of the BEMF signal regardless of minor variations in the location of the BEMF signals, or timing of the BEMF signals due to varying speeds of spindle rotation, thereby insuring the proper control of the spindle motor.