Phase locked loop for synchronizing with carrier wave

Abstract

A phase locked loop circuit for synchronizing with carrier wave includes: a variable divider for generating a first reference signal and a second reference signal whose frequency is same as the frequency of the first reference signal and whose phase is shifted by 90 degrees with respect to the phase of the first reference signal, the variable divider varying the frequencies of the first reference signal and the second reference signal in accordance with a control signal; a first multiplier for multiplying an input signal by the first reference signal; an exclusive OR circuit for operating an exclusive OR of the input signal and the output signal of the first multiplier; a phase comparator for receiving the first reference signal, the second reference signal and the output signal of the exclusive OR circuit, and detecting a value and a direction of a phase difference between the input signal and the first reference signal to produce phase comparison signal including series of clock pulses whose number corresponding to the value of the phase difference and indicative of the direction of the phase difference; and a loop filter for producing the control signal on the basis of the phase comparison signal.