The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 1995
Filed:
May. 09, 1994
Toshiharu Katayama, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A DRAM having a stacked-type capacitor whose structure has a capacitor lower electrode, a first impurity region connected thereto, a third impurity region formed by thermal diffusion of impurities included in the capacitor lower electrode, is disclosed in which an end portion of a third impurity region on the side of gate electrode can be effectively prevented from being extended from an end portion of a first impurity region on the side of gate electrode in the subsequent heat treatment. In the DRAM, an epitaxial silicon layer 8 or a polycrystalline silicon layer 28 having an impurity concentration lower than that of capacitor lower electrode 9 is interposed between capacitor lower electrode 9 and a first impurity region 3b, so that thermal diffusion of impurities in capacitor lower electrode 9 is reduced as compared with the conventional case. As a result, the end portion of the third impurity region which is formed by thermal diffusion on the side of the gate electrode is not extended from the end portion of the first impurity region on the side of the gate electrode, and an effective gate length is not shortened. Hence, a short channel effect and a punch through phenomenon can be effectively prevented.