The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 1995

Filed:

Aug. 09, 1993
Applicant:
Inventors:

Daniel Brasen, Lake Hiawatha, NJ (US);

Eugene A Fitzgerald, Jr, Bridgewater, NJ (US);

Martin L Green, New Providence, NJ (US);

Donald P Monroe, Berkeley Heights, NJ (US);

Paul J Silverman, Millburn, NJ (US);

Ya-Hong Xie, Flemington, NJ (US);

Assignee:

AT&T Corp., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257191 ; 257 12 ; 257 18 ; 257 19 ; 257 20 ; 257 21 ; 257 22 ; 257 24 ; 257 27 ; 257 54 ; 257 55 ; 257183 ; 257190 ; 257192 ;
Abstract

A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.


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