Data processor having branch predicting function

Abstract

An instruction loaded in an instruction register is decoded by an instruction decoder and the branch predicting bit which indicates whether the instruction is branched or not is read out from a branch predicting mechanism. If it is determined that the instruction is a conditional branch instruction as a result of decoding and the instruction is branched as a result of branch prediction, an instruction length and a branch displacement are replaced with each other by a selector, the branch displacement is added to a decoding program counter, and an address of the branch target destination is designated. On the other hand, in an object computer, the branch displacement of the conditional branch instruction is replaced with the instruction length of the conditional branch instruction, the branch condition is inverted, and the changed conditional branch instruction is executed. If the original branch prediction that a branch would occur with respect to the conditional branch instruction was wrong, the changed conditional branch instruction is executed in the object computer and branched, so that an instruction located subsequently to the conditional branch instruction on the program can be fetched particularly without requiring a mechanism for fetching again the instruction.