The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 1995
Filed:
Jul. 08, 1994
Tatsuya Ishikawa, Yokohama, JP;
Noboru Taga, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A QPSK modulated wave is inputted to an in-phase detector and an orthogonal detector. The detected components are converted to substantially a base band, and each component is digital-converted by A/D converters. Each digital component is spectrum-shaped by digital LPFs. The outputs of digital LPFs are inputted to a complex multiplier and calculated by use of first and second reproduction carriers and expressed as first and second calculation outputs, and inputted to a phase detector. The phase detector obtains phase difference data between the phase expressed by the first and second calculation outputs and a predetermined phase and quadrant data of the phase. The phase difference data is used for a PLL. The phase difference data is is inputted to a frequency error detection circuit detecting a frequency error. The frequency error output is smoothed by a filter of an AFC loop, and used as a control signal controlling the oscillation frequency of the local oscillation unit. If the frequency error is large, the frequency error detection circuit controls the AFC loop to be in an operation state and the PLL loop and the PLL loop to be in a fixed state. If the frequency error is small, the frequency error detection circuit contains the control state of the AFC loop and switches the PLL loop to be the operation state.