Extended architecture for fpga

Abstract

The invention provides a packaging technique implementing an electronic circuit, comprising several individually packaged sub-circuits, on a circuit board within the footprint of a single package. The embodiment of the present invention is particularly advantageous when implementing application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Selected pins of an upper package are electrically coupled to corresponding pins of the next lower adjacent package such that the pins of the uppermost package can be coupled to the pins of the lowermost package and correspondingly to the signal leads and power bus conductors of the printed circuit board. Portions of selected pins may be removed from one or more packages prior to forming the stacked structure to electrically isolate corresponding pins of upper packages from the pins of lower packages. A template is provided that permits rapid identification of pins to be removed before the packages are configured in the stack. Careful partitioning of the electrical circuit permits a limited number of standard bonding patterns to be combined in a large variety of configurations by rotating packages relative to adjacent packages in the stack. Each package is also provided with additional pins that may be used for vertical routing in a manner that couples non-adjacent packages without coupling to intervening packages. Heat sinks and heat pipes are attachable to the stack to increase thermal dissipation.