The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 1995
Filed:
May. 03, 1994
Douglas W Schucker, Mesa, AZ (US);
Walter C Seelbach, Fountain Hills, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.